This invention relates to a drive circuit incorporated in a touch screen and a display circuit. More particularly, the drive circuit includes circuitry for driving a plurality of logic gates that are connected in parallel, wherein each of which consume a short circuit current during a logic state transition.
Complementary metal-oxide semiconductor (CMOS) is a technology for constructing digital logic circuits and for several analog circuits such as image sensors, data converters and transceivers used in many types of communication. CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for implementing logic functions. An example of a circuit 2 that performs an inverting or NOT function is shown in FIG. 1A. In the inverting circuit 2, an input 4 is connected to both a PMOS transistor 6 and an NMOS transistor 8. When the voltage at the input 4 is low, the channel of the NMOS transistor 8 is in a high resistance state. This limits the current that can flow from an output 10 to ground. The channel of the PMOS transistor 6 is, however, in a low resistance state and much more current can flow from a supply 12 to the output 10. Because the resistance between the supply 12 and the output 10 is low, the voltage drop between the supply 12 and the output 10 due to a current drawn from the output 10 is small. The output 10 therefore registers a high voltage.
Conversely, when the voltage of the input 4 is high, the PMOS transistor 6 is in an OFF (high resistance) state, thereby limiting the current flowing from the supply 12 to the output 10, whereas the NMOS transistor 8 is in an ON (low resistance) state, thereby allowing the output 10 to drain to ground. Because the resistance between the output 10 and ground is low, the voltage drop due to a current drawn into the output placing the output above ground is small. This low drop results in the output 10 registering a low voltage. In summary, the output of the PMOS and NMOS transistors 6 and 8 are complementary such that when the input 4 is low, the output 10 is high, and when the input 4 is high, the output 10 is low. Because of this behavior of the input 4 and output 10, the CMOS circuit's output 10 is the inversion of the input 4.
As illustrated in FIG. 1B, there is a finite rise/fall time in the input signal 14 when it transitions between off and on because of the capacitance of the PMOS and the NMOS transistors 6 and 8. During this transition, both the transistors 6 and 8 will be on for a small period of time, and the current will flow directly from the supply 12 to ground, resulting in a short circuit current 16 as shown in FIG. 1B. This is typically the case in the digital domain where the supply voltage Vdd is higher than the combination of the threshold voltages of the PMOS and NMOS transistors, Vth(P) and Vth(N) respectively. It is also the case for logic functions created in the analog domain when the analog supply voltage Vdd is higher than the combination of the threshold voltages of the PMOS and NMOS transistors, Vth(P) and Vth(N) respectively. It should be understood that the threshold voltage of a transistor is the gate-source voltage at which the drain current reaches some defined small value. As shown in FIG. 1B, the short circuit current 16 through a single pair of PMOS and NMOS transistors may not be significant. However, as shown in FIGS. 2A and 2B, when there are many such transistor pairs 6A, 6B, 6C connected in parallel, there is an increase in capacitance of the transistors that will result in an even slower rise/fall time of a signal 18 at an input 4A. Consequently, the short circuit current 20 flowing through the transistor pairs 6A, 6B, 6C is increased both in magnitude and duration as shown in FIG. 2B.
Typically, a regulator circuit is connected to the transistor pairs to supply voltage and current to the transistor pairs. The short circuit current results in a large spike in the supply current. This may result in a drop in the supply voltage. In some embodiments, to avoid such a condition, a decoupling capacitor may be connected across the output of the regulator. Additionally or alternatively, a larger and more powerful regulator may be used in other embodiments. However, since space is limited on some circuit boards, the addition of a decoupling capacitor or the use of a larger regulator may not be possible. Therefore, there exists a need to provide drive circuitry that does not require the use of a decoupling capacitor or large regulator to reduce the current spike.